Various parameters in the design of an integrated circuit, or chip, have a significant dependence on power supply voltage. Examples of such parameters are delay values in static timing analysis and extreme voltage drop values. Variations in power supply and ground voltages between driving and receiving gates can also have an impact on such parameters.
The power supply and ground voltages will vary both spatially (across different locations on the chip) and temporally (in time). Given an average current demand at each location on the chip and an electrical (resistive) model of the chip and package power distribution network, various known power bus simulation methods may be used to determine average (non-time varying) power supply and ground voltages at different locations on the chip. Similarly, if time varying current demand waveforms for each location on the chip are provided along with an electrical (L, R, C) model of the chip and package power distribution network and decoupling capacitances, power supply simulation methods can compute corresponding voltage waveforms at different locations on the chip.
Average voltage values may be input to static timing analysis by using a different voltage (or set of supply, ground, driver supply, and driver ground voltages) in calculating delays for each circuit element, or block of circuit elements, on the chip. In an alternative, voltage waveforms may also be used in static timing analysis, but this requires sampling of the voltage (or voltages) for each circuit element at the time the signal transition is propagating through the block. In one existing commercial tool a first timing analysis is done to determine times during which each gate makes its critical transition(s). A second timing analysis is done in which the arrival times from the first analysis are used to determine the time at which the voltage waveform for a block should be sampled for use in delay calculation. The procedure is repeated, using arrival times from the most recent analysis to determine when to sample voltage waveforms to compute the delays for the next analysis. This iterative analysis can be inefficient.
A key problem is determining which conditions (and hence which average current demand or current demand waveforms) are the worst condition for timing. One method is to try to determine the maximum current demand subject to some constraints. A typical constraint is that the percentage of signals switching in any cycle does not exceed some bound. There may be both a global bound and a higher local bound for regions of a given size (e.g., no more than 15% of all chip nets switch, and no more than 30% of the nets in any 1 mm by 1 mm region switching in any cycle). Various heuristics are then used to try to determine a “worst case” switching scenario given these constraints.
A problem with this approach is that the maximum power condition may not cause the minimum timing margin. Most timing requirements on a chip are setup or hold tests at memory elements (e.g., flip-flops or latches), and constitute a comparison between a clock and data arrival time at the memory element. For a setup test the requirement is that the latest possible data transition in a cycle arrive at least a specified time before the earliest possible clock signal. For a hold test the requirement is that the earliest possible data transition in a cycle arrive at least a specified time before the latest possible clock signal. Thus, the worst case switching condition (and resulting voltage waveform) for a timing test is the one which causes the maximum change in the difference between a late signal arrival time and an early signal arrival time. Further, this method uses heuristics which give no guarantee that the maximum voltage reduction condition for blocks along any given path was actually discovered.
In addition to determining the impact that voltage fluctuations have on chip timing, it is desirable to understand the extreme voltage values which can occur at different locations within the power distribution network on a chip.
Previous methods for computing voltage bounds apply a particular set of current waveforms to the various nodes of the power supply network (possibly over many clock cycles), perform simulation to produce resultant voltage waveforms at each of the power bus nodes, and then determine extreme values of those voltage waveforms. The set of current waveforms applied model the current demand associated with a particular chosen pattern of activity for the various elements on the chip. This method is limited, in that the length of current waveform required to consider all possible patterns of current demand is extremely long. For example, if there are 10 different objects on the chip which can draw current in a particular waveform and current drawn in a particular clock cycle can affect the power supply node voltages for up to three cycles, a total of 2(10*3) (=230) or over 1 billion cycles of current waveform must be simulated to consider all possible activity patterns. This is clearly prohibitive, and thus a more efficient means of determining extreme voltages is needed.